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Semiconductor device and method of manufacturing the same

Patent 6603191 Issued on August 5, 2003. Estimated Expiration Date: Icon_subject May 15, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal
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Semiconductor device and method for manufacturing the same
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Semiconductor device and method of manufacturing the same
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Issued on: 11/23/1999
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Method for constructing a leadless array package
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Semiconductor device using a chip scale package
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Method of manufacturing resin encapsulated semiconductor device
Patent #: 6174751
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Semiconductor device with economical compact package and process for fabricating semiconductor device
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Resin overmolded type semiconductor device
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Issued on: 07/24/2001
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6321734

Inventors

Assignee

Application

No. 858230 filed on 05/15/2001

US Classes:

257/620, With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area)257/738, Ball shaped257/778, Flip chip257/795, With specified filler material257/E21.502, Encapsulation, e.g., encapsulation layer, coating (EPO)257/E21.508, Forming solder bumps (EPO)257/E23.021, Bump or ball contacts (EPO)257/E23.124Device being completely enclosed (EPO)

Examiners

Primary: Elms, Richard
Assistant: Menz, Douglas

Attorney, Agent or Firm

Foreign Patent References

  • 0 706 208 EP. 04/12/1996
  • 0 853 337 EP. 07/12/1998
  • 8-70081 JP. 03/12/1996
  • 11-121507 JP. 04/12/1999
  • 11-224890 JP. 08/12/1999

International Class

H01L 023/544

Foreign Application Priority Data

2000-05-18 JP

Abstract

The back surface of a semiconductor wafer having a plurality of chip-forming regions each provided with a plurality of connection pads on the surface is bonded to a dicing tape, followed by fully cutting the semiconductor wafer along a cut line so as to form a cutting groove. Then, a front side protective film is formed on the front surface. The front side protective film has an open portion exposing the central portion of the connection pad, and is filled in the cutting groove. After formation of a columnar electrode connected to the connection pad via a wiring, a sealing film is formed on the front side protective film. Further, the cutting groove filled with the front side protective film is cut in substantially the center in the width direction, followed by peeling off the dicing tape so as to form individual semiconductor devices each forming a chip.

Other References

  • Masatoshi Yasunaga et al: "Chip Scale Package* (CSP) A Lightly Dressed LSI Chip", Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology Symposium, New York, U.S., IEEE vol. Symp. 16, pp. 169-176 XP000530088, ISBN: 0-7803-2038-7, p. 169-p. 171; Figures 1-
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