Abstract

Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency.

Other References

• Halter S, et al. "Reconfigurable signal Processor for Channel Cording & Decoding in Low SNR Wireless Communications." IEEE Workshop in Signal Processing Systems, SIPS, Design and Implementation, Oct. 8, 1998, pp. 260-274
• Hsu J-M, et al. "A Parallel Decoding Scheme for Turbo Codes." ISCAS 1998. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA, May 31-Jun. 3, 1998, New York, NY: IEEE, US, vol. 1, May 31, 1998, pp. 445-448
• Schurgers, et al. "Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module." Proceedings 1999 International Symposium on Low Power Electronics and Design. San Diego, CA, Aug. 16-17, 1999, International Symposium on Low Power Electronics and Design, New York, NY: ACM, US, Aug. 16, 1999, pp. 76-81
• Viterbi A. J., "An Intuitive Justification and a Simplified Implementation of the Map Decoder for Convolutional Codes," IEEE Journal on Selected Areas in Communications, IEEE Inc., New York, US vol. 16, No. 2, Feb. 1, 1998, pp. 260-264
• European Search Report. Application No. EP 00 20 0557. Date of Completion, May 28, 2002
• Joeressen, et al., "High-Speed VLSI Architectures for Soft-Output Viterbi Decoding", vol. 8, No. 2, 1994 pps. 169-181
• Garrett, et al., "Low Power Architecture of the Soft-Output Viterbi Algorithm", ISLPED 1998, pps. 262-267
• Berrou, et al., Near Shannon Limit Srror-Correcting Coding and Decoding: Turbo-Codes (1), IEEE, 1993, pps. 1064-1070
• S. Pietrobon, "Efficient Implementation of Continuous MAP Decoders and a Synchronisation Technique for Turbo Decoders", Int. Symp. on Inform. Theory and its Applications, Sep. 1996, pps. 586-58