U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Fibre channel host bus adapter having multi-frequency clock buffer for reduced power consumption

Patent 6594275 Issued on July 15, 2003. Estimated Expiration Date: Icon_subject September 25, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Circuit for use either as a serial-parallel converter and multiplexer or a parallel-serial converter and demultiplexer in digital transmission systems
Patent #: 4157458
Issued on: 06/05/1979
Inventor: Roche

Serial-to-parallel converter using alternating latches and interleaving techniques
Patent #: 5648776
Issued on: 07/15/1997
Inventor: Widmer

Serial to parallel converter enabled by multiplexed flip-flop counters
Patent #: 6052073
Issued on: 04/18/2000
Inventor: Carr, et al.

Serial to parallel and parallel to serial, converter for a digital audio workstation
Patent #: 6128681
Issued on: 10/03/2000
Inventor: Shephard

Adjustable serial-to-parallel or parallel-to-serial converter Patent #: 6169501
Issued on: 01/02/2001
Inventor: Ryan

Inventor

Assignee

Application

No. 160920 filed on 09/25/1998

US Classes:

370/465, Adaptive370/503, Synchronizing370/537Multiplexing plural input channels to a common output channel

Examiners

Primary: Hsu, Alpus H.
Assistant: Tran, Thai

Attorney, Agent or Firm

International Class

H04J 003/16

Abstract

A Fiber Channel host bus adapter has a low power, high speed serial to parallel data converter for converting asynchronous serial data into clock aligned, framed, parallel data utilizing a serial in, parallel out register for receiving asynchronous serial data and for providing unframed parallel data. An array of parallel in, parallel out registers is configured to receive parallel data from the serial in, parallel out data register and move the data in a parallel fashion between the parallel in, parallel out registers thereof. A pattern detection circuit identifies a location of a delimiter character within the array of a parallel in, parallel out registers. A selection circuit reads desired data bits from the array of parallel in, parallel out registers in a parallel fashion, based upon the location of the delimiter character, to define a framed parallel output word. A data alignment circuit aligns the framed parallel output word with respect to a clock to define a clock aligned, framed parallel output word.

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