Method for ensuring maximum bandwidth on accesses to strided vectors in a bank-interleaved cache
Patent 6591345 Issued on July 8, 2003. Estimated Expiration Date: 
November 28, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 28, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements Method and system in a data processing system for loading and storing vectors in a plurality of modes Low-power memory system with incorporated vector processing Patent #: 6311280 InventorAssigneeApplicationNo. 723825 filed on 11/28/2000US Classes:711/127, Interleaved711/129, Partitioned cache711/168Concurrent accessingExaminersPrimary: Portka, GaryInternational ClassG06F 012/02AbstractA system and method is disclosed that reduces intrabank conflicts and ensures maximum bandwidth on accesses to strided vectors in a bank-interleaved cache memory. The computer system contains a processor including a vector execution unit, scalar processor unit, cache controller and bank-interleaved cache memory. The vector execution unit retrieves strided vectors of data and instructions stored in the bank-interleaved cache memory in a plurality of cache banks such that intrabank conflicts are reduced. Given a stride S of a vector, the strided vectors of data and instructions stored in the bank-interleaved cache memory are retrieved by determining R and T using the equation S=2T *R. If T<=W, W defining a cache bank 2W words wide, then, for 0<=i<2.sup.(W-T), 0<=j<2P, and 0<=k<2N, words addressed i+2.sup.(W-T+N) j+2.sup.(W-T) k are accessed on the same cycle. P defines the bank-interleaved cache memory to contain 2P sets and N defines 2N cache banks in one set of the bank-interleaved cache memory. If W<T<N, then for 0<=j<2P and 0<=k=N, then the vector words are accessed sequentially at different cycles.Other References
Field of SearchInterleavedPartitioned cache Shared cache Multiport cache Concurrent accessing Including plural logical address spaces, pages, segments, blocks Generating a particular pattern/sequence of addresses Vector processor Scalar/vector processor interface Controlling access to external vector data Vector processor operation | |
