U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Semiconductor die package with improved thermal and electrical performance

Patent 6566749 Issued on May 20, 2003. Estimated Expiration Date: Icon_subject January 15, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Package for push-pull semiconductor devices
Patent #: 4193083
Issued on: 03/11/1980
Inventor: Max

Hybrid transistor
Patent #: 4213141
Issued on: 07/15/1980
Inventor: Colussi

Hybrid transistor
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Issued on: 07/12/1983
Inventor: Hale

Power MOSFET
Patent #: 5095343
Issued on: 03/10/1992
Inventor: Klodzinski, et al.

Transistor package
Patent #: 5309014
Issued on: 05/03/1994
Inventor: Wilson

Package for semiconductor elements having thermal dissipation means
Patent #: 5455457
Issued on: 10/03/1995
Inventor: Kurokawa

Power module using IMS as heat spreader
Patent #: 5513072
Issued on: 04/30/1996
Inventor: Imaji, et al.

Package for a power semiconductor die and power supply employing the same
Patent #: 5872403
Issued on: 02/16/1999
Inventor: Bowman, et al.

RF power package with a dual ground
Patent #: 5889319
Issued on: 03/30/1999
Inventor: Moller, et al.

Lateral MOS transistor with weakly doped drain extension
Patent #: 6020617
Issued on: 02/01/2000
Inventor: Jos

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Inventors

Application

No. 050428 filed on 01/15/2002

US Classes:

257/706, With heat sink257/589, Avalanche transistor257/678, HOUSING OR PACKAGE257/712, With provision for cooling the housing or its contents257/784, Wire contact, lead, or bond257/E21.512, Right-up bonding (EPO)257/E23.104, Characterized by shape of housing (EPO)257/E23.181Characterized by shape of container or parts, e.g., caps, walls (EPO)

Examiners

Primary: Fahmy, Wael
Assistant: Nguyen, Dinh Q.

Attorney, Agent or Firm

International Classes

H01L 023/10
H01L 023/34

Abstract

A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.

Other References

  • Wood et al., "High Performance Silicon LDMOS Technology for 2GHz RF Power Amplifier Applications,"IEEE, pp. 4.2.1-4.2.4, 0-7803-3393-4 (1996
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