System and method for recovering from design errors in integrated circuits
Patent 6553548 Issued on April 22, 2003. Estimated Expiration Date: 
December 14, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 14, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of analyzing logic circuit test points, apparatus for analyzing logic circuit test points and semiconductor integrated circuit with test points Method for improving fault coverage of an electric circuit Patent #: 6059451 InventorApplicationNo. 460843 filed on 12/14/1999US Classes:716/5, Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)716/4, Testing or evaluating716/6Timing analysis (e.g., delay time, path delay, latch timing)ExaminersPrimary: Smith, MatthewAssistant: Levin, Naum Attorney, Agent or FirmInternational ClassG06F 009/45AbstractThe present invention is embodied in a system and method for recovering from design errors, such as errors in an integrated circuit design. The system and method of the present invention use a probabilistic model, such as a Bayesian Belief Network (BBN), in combination with case-based inferential reasoning to predict or detect design errors at any point in the design process by using information about the current design in combination with historical design error data from previous designs. Once conditions associated with design errors are predicted or detected, an error profile is generated. An inference engine then uses conditional probabilities produced by the probabilistic model to compile a set of exact or similar cases from a historical knowledge base containing solutions and workarounds to previously identified design errors, based on their probable relevancy to the current design case. These probable relevant cases are then presented to the user, ranked with their likelihood or probability of relevance to the current predicted or detected design error. These cases are preferably presented to the user both textually and graphically in an interactive computer program environment.Field of SearchDESIGN OF SEMICONDUCTOR MASKGlobal routing (e.g., shortest path, dead space, or duplicate trace elimination) Translation (e.g., conversion, equivalence) Floorplanning Logical circuit synthesizer Testing or evaluating Routing (e.g., routing map, netlisting) Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width) Timing analysis (e.g., delay time, path delay, latch timing) Pattern exposure PLA, PLD, FPGA, OR MCM PCB wiring Optimization (e.g., redundancy, compaction) Detailed placement (i.e., iterative improvement) Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) Partitioning (e.g., function block, ordering constraint) Detailed routing (e.g., channel routing, switch box routing) CIRCUIT DESIGN Layout editor (e.g., updating) Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance) Mesh generation Particular stimulus creation Scan path testing (e.g., level sensitive scan design (LSSD)) Signature analysis Built-in testing circuit (BILBO) Structural (in-circuit test) Including test pattern generator Simulation Fault recovery Probability determination Cause or fault identification History logging or time stamping Circuit simulation Integrated circuit production or semiconductor fabrication | |
