U.S. patents available from 1976 to present.
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Complete CDS/PGA sample and hold amplifier

Patent 6529237 Issued on March 4, 2003. Estimated Expiration Date: Icon_subject November 10, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Charge amplifier for MOS imaging array and method of making same
Patent #: 5724095
Issued on: 03/03/1998
Inventor: Shyu, et al.

Correlated double sampling method and apparatus
Patent #: 6018364
Issued on: 01/25/2000
Inventor: Mangelsdorf

Sensing circuit for capturing a pixel signal
Patent #: 6166766
Issued on: 12/26/2000
Inventor: Moore, et al.

Analog current mode assisted differential to single-ended read-out channel operable with an active pixel sensor
Patent #: 6201572
Issued on: 03/13/2001
Inventor: Chou

Color balancing circuit and method Patent #: 6346968
Issued on: 02/12/2002
Inventor: Domer, et al.

Inventors

Assignee

Application

No. 189237 filed on 11/10/1998

US Classes:

348/241, Including noise or undesired signal reduction348/243, Dark current348/308, Including switching transistor and photocell at each pixel site (e.g., "MOS-type" image sensor)348/533Noise reduction

Examiners

Primary: Garber, Wendy R.
Assistant: Ye, Lin

Attorney, Agent or Firm

International Classes

H04N 005/217
H04N 009/64
H04N 005/335
H04N 005/08

Abstract

A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch (34) to clamp the DC level therein for a given pixel. A switch (38) then samples the reset level onto a sampling capacitor (46), and a switch (42) thereafter samples the video signal onto one plate of a capacitor (50). The lower plates of the capacitors (46) and (50) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier (68). An offset is provided by a programmable DAC (26) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors (46) and (50) can be varied to vary the gain of the amplifier.

Other References

  • Matsumoto et al. A CMOS fron-end for CCD cameras, IEEE, pp. 186-187, 1996.
  • Hyabg et al., Reduced nonlinear distortion in circuits with correlated double sampling, IEEE, pp. 159-162, 1996.
  • Wang et al., Capacitive ration testing and sensor readout, IEEE, pp. 1169-1172, May 19-21, 199
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