Method for verifying the design of a microprocessor

Patent 6523151 Issued on February 18, 2003. Estimated Expiration Date:

May 17, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method for measuring architectural test coverage for design verification and building conformal test Patent #: 5724504
Issued on: 03/03/1998
Inventor: Aharon, et al.

Inventor

Hekmatpour, Amir

Application

No. 859250 filed on 05/17/2001

US Classes:

716/4, Testing or evaluating716/5Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)

Examiners

Primary: Thomas, Tom
Assistant: Tran, Thai

Attorney, Agent or Firm

Lally; Joseph P., Tyson; Tom, Emile; Volel

International Class

G06F 017/50

Abstract

A method for verifying an integrated circuit design includes generating verification coverage information by simulating the operation of the integrated circuit. The verification coverage information is then analyzed to determine a set of missing coverage states. A set of verification directives based on the set of missing coverage states is composed and a set of test cases is generated, based on the verification directives, to simulate the missing coverage states. Analyzing the verification coverage information may include decomposing the verification coverage information into a set of basic coverage tasks (BCTs), wherein each BCT is a generic representation of a corresponding task. Decomposing the verification coverage information into a set of BCTs may comprise decomposing the verification coverage information into a set of covered BCTs and a set of BCT holes, wherein the covered BCTs represent verification states covered by the simulation and BCT holes represent verification states not covered.