Copper interconnect methodology for enhanced electromigration resistance
Copper interconnection structure incorporating a metal seed layer
Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
Self-encapsulated copper metallization
Copper alloy electroplating bath for microelectronic applications
Metallization structures for microelectronic applications and process for forming the structures Patent #: 6368966
ApplicationNo. 016410 filed on 12/07/2001
US Classes:257/762, At least one layer containing silver or copper257/751, At least one layer forms a diffusion barrier257/752, Planarized to top of insulating layer257/767, Resistive to electromigration or diffusion of the contact or lead material257/775, Varying width or thickness of conductor257/E23.145Via connections in multilevel interconnection structure (EPO)
ExaminersPrimary: Whitehead, Carl Jr.
Assistant: Smoot, Stephen W.
Attorney, Agent or Firm
International ClassH01L 023/532
AbstractA method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu--Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu--Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu--Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.