Method and apparatus for placing repeaters in a network of an integrated circuit
Patent 6493854 Issued on December 10, 2002. Estimated Expiration Date: 
October 1, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 1, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of minimizing area for fanout chains in high-speed networks Stable delay buffer Digital buffer circuits Patent #: 6163174 InventorsAssigneeApplicationNo. 411725 filed on 10/01/1999US Classes:716/6, Timing analysis (e.g., delay time, path delay, latch timing)716/2, Optimization (e.g., redundancy, compaction)716/8, Floorplanning716/10, Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)716/12, Routing (e.g., routing map, netlisting)716/18Logical circuit synthesizerExaminersPrimary: Smith, MatthewAssistant: Do, Thuan Attorney, Agent or FirmInternational ClassG06F 017/50AbstractA method of inserting repeaters into a network to improve timing characteristics of the network. Extraction and timing tools provide an RC network description and a slack report describing electrical and timing characteristics of a network. The timing characteristics include required arrival times of a signal generated at a source to each of the sinks of the network. A maximum slew rate is also defined at each of the sinks. Initial candidate locations for insertion of repeaters is determined. For a given set of legal repeater sizes, one or more sets of midvalue repeater sizes are determined which are used in successive approximation to identify actual repeater sizes to be considered at each of the candidate locations. At each candidate location, capacitance, required arrival time, and slew rate value (c, q, s) are determined in a bottom-up procedure. Suboptimal and invalid (c, q, s) choices at each candidate location are eliminated during successive iterations of the bottom-up procedure until the source node is reached. Further, one or more of the candidate locations are also eliminated. When the source device is reached, the (c, q, s) values are determined at the source for the given size of the source. The particular combination of (c, q, s) values at the descendant nodes relative to the source that provide a maximum q value at the source are selected, and this procedure is repeated in a top-down traversal to identify the best solution for the net for the particular repeater sizes being used.Other References
Field of SearchCMOSIncluding significant compensation (e.g., temperature compensated delay, etc.) Optimization (e.g., redundancy, compaction) Timing analysis (e.g., delay time, path delay, latch timing) Floorplanning Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance) Routing (e.g., routing map, netlisting) Detailed routing (e.g., channel routing, switch box routing) Logical circuit synthesizer | |
