U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Ferroelectric memory device

Patent 6483737 Issued on November 19, 2002. Estimated Expiration Date: Icon_subject September 21, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Non-volatile memory cell and sensing method
Patent #: 4888733
Issued on: 12/19/1989
Inventor: Mobley

Symmetrical polarization enhancement in a ferroelectric memory cell
Patent #: 5309391
Issued on: 05/03/1994
Inventor: Papaliolios

Semiconductor memory device and various systems mounting them
Patent #: 5903492
Issued on: 05/11/1999
Inventor: Takashima

Nonvolatile ferroelectric memory
Patent #: 5943256
Issued on: 08/24/1999
Inventor: Shimizu, et al.

Ferroelectric memory and screening method therefor
Patent #: 6046926
Issued on: 04/04/2000
Inventor: Tanaka, et al.

Semiconductor memory device utilizing a polarization state of a ferroelectric film
Patent #: 6154387
Issued on: 11/28/2000
Inventor: Takata

Non-volatile semiconductor integrated memory device Patent #: 6198652
Issued on: 03/06/2001
Inventor: Kawakubo, et al.

Inventors

Assignee

Application

No. 956938 filed on 09/21/2001

US Classes:

365/145, Ferroelectric365/117, Ferroelectric365/149Capacitors

Examiners

Primary: Nelms, David C.
Assistant: Le, Thong

Attorney, Agent or Firm

International Class

G11C 011/22

Foreign Application Priority Data

2000-10-17 JP

Abstract

A ferroelectric memory device comprises a word line, first and second bit lines cross to the word line, a memory cell including a first transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the first bit line, a second transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the second bit line, and a ferroelectric cell capacitor coupled to the other of source and drain of the first and second transistor, and first and second capacitors each coupled via a switching transistor to a respective one of the first and second bit lines, wherein first and second voltages complementary to each other are applied to the first and second bit lines, via the first and second capacitors, respectively.

Other References

  • D. Takashima et al., "A Sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive", ISSCC99/ Session 6/ Paper MP 6.1, pp. 102-103 199
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