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Semiconductor device and method of manufacturing the same

Patent 6483151 Issued on November 19, 2002. Estimated Expiration Date: Icon_subject January 4, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit Patent #: 6255698
Issued on: 07/03/2001
Inventor: Gardner, et al.

Inventors

Assignee

Application

No. 754637 filed on 01/04/2001

US Classes:

257/369, Complementary insulated gate field effect transistors257/407, With gate electrode of controlled workfunction material (e.g., low workfunction gate material)257/412, Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal)257/915WITH TITANIUM NITRIDE PORTION OR REGION

Examiners

Primary: Prenty, Mark V.

Attorney, Agent or Firm

Foreign Patent References

  • 06-005852 JP. 01/20/1994
  • 09-148455 JP. 06/20/1997
  • 11-224947 JP. 08/20/1999
  • 11-307729 JP. 11/20/1999

International Class

H01L 029/76

Foreign Application Priority Data

2000-01-21 JP

Abstract

One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.

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