Process for creating vias using pillar technology
Trench dram cell with vertical device and buried word lines Patent #: 5977579
ApplicationNo. 789939 filed on 02/12/2001
US Classes:438/574, T-shaped electrode438/576, Into grooved or recessed semiconductor region438/578Forming electrode of specified shape (e.g., slanted, etc.)
ExaminersPrimary: Nelms, David C.
Assistant: Berry, Renee R.
Attorney, Agent or Firm
International ClassH01L 021/44
AbstractFor fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second side surfaces, and the pillar has a width, a length, and a height. A masking structure is formed on a center portion of the top surface of the pillar along the length of the pillar. A top portion of the height of the pillar is etched from exposed surfaces of the top surface of the pillar down to a bottom portion of the height of the pillar to form an upside down T-shape for the pillar. A gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar for a gate length along the length of the pillar. A gate electrode material is deposited on the gate dielectric material to surround the pillar for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar. In this manner, for a given height and width of the semiconductor pillar, any point of a cross-section of such a pillar is more closely located to the gate bias applied at a surface of such a pillar to maximize effective drive current while minimizing undesired short channel effects of the field effect transistor.