U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Configurable processor system unit

Patent 6467009 Issued on October 15, 2002. Estimated Expiration Date: Icon_subject October 14, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

On chip ram interconnect to MPU bus
Patent #: 4314353
Issued on: 02/02/1982
Inventor: Gunter ,   et al.

Programmable array logic cell
Patent #: 4789951
Issued on: 12/06/1988
Inventor: Birkner ,   et al.

Configurable electrical circuit having configurable logic elements and configurable interconnects
Patent #: 4870302
Issued on: 09/26/1989
Inventor: Freeman

Method for selectively loading bootable fiber to control apparatus based upon the corresponding bootable attributes
Patent #: 5093915
Issued on: 03/03/1992
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Programmable connector for programmable logic device
Patent #: 5140193
Issued on: 08/18/1992
Inventor: Freeman, deceased, et al.

Address control and generating system for digital signal-processor
Patent #: 5206940
Issued on: 04/27/1993
Inventor: Murakami, et al.

RE34363

Distributed memory architecture for a configurable logic array and method for using distributed memory
Patent #: 5343406
Issued on: 08/30/1994
Inventor: Freeman, et al.

Page register with a don't care function
Patent #: 5347641
Issued on: 09/13/1994
Inventor: Cedar, et al.

Programmable logic device with redundant circuitry
Patent #: 5369314
Issued on: 11/29/1994
Inventor: Patel, et al.

More ...

Inventors

Application

No. 172918 filed on 10/14/1998

US Classes:

710/305, Bus interface architecture710/306, Bus bridge710/308, Direct memory access (e.g., DMA)710/309, Arbitration712/10, Array processor712/15, Reconfiguring712/29, Interface712/31, Master/slave712/36Application specific

Examiners

Primary: Wong, Peter S.
Assistant: Phan, Raymond N

Attorney, Agent or Firm

Foreign Patent References

  • 0062431 EP 03/13/1982
  • 0139254 EP 09/13/1984
  • 0307649 EP 08/13/1988
  • 0306962 EP 09/13/1988
  • 0361525 EP 09/13/1989
  • 0486248 EP 11/13/1991
  • 0503498 EP 03/13/1992
  • 0511674 EP 04/13/1992
  • 0536793 EP 10/13/1992
  • 0636976 EP 07/13/1994
  • 0742516 EP 04/13/1996
  • 2297409 GB 01/13/1996

International Class

G06F 001/00

Abstract

The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

Other References

  • PCT Search Report, PCT/US99/24114, dated Jan. 26, 2000, 5 pgs
  • PCT Search Report, PCT/US99/24114, dated Apr. 25, 2000, 10 pgs
  • Efficient Mechanism for Multiple Debug Modes, IBM Technical Disclosure Bulletin, vol. 38, No. 11, Nov. 1995, pp. 65-68
  • System Master Slice For Fast Turnaround Time, IBM Technical Disclosure Bulletin, vol. 26, No. 3B, Aug. 1983, pp. 1531-1532
  • Update Mechanism For Personal Computer System Resident Firmware, IBM Technical Disclosure Bulleten, vol. 34, No. 10B, Mar. 1992, pp. 133-13
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