Compensation circuit for low phase offset for phase-locked loops
July 22, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3725793 Phase detector with independent offset correction Clock circuit having a clocked output buffer Clock selection circuit for selecting one of a plurality of clock pulse signals High speed on-chip clock phase generating system Clock distribution system and technique Programmable secondary clock generator Skew-free clock signal distribution network in a microprocessor Phase-locked loop circuit Dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction InventorsApplicationNo. 359952 filed on 07/22/1999US Classes:327/156, Phase lock loop147/7, Miscellaneous327/147, Phase lock loop327/159, With digital element327/362, With compensation331/1AAFC with logic elementsExaminersPrimary: Le, Dinh T.Attorney, Agent or FirmForeign Patent References
International ClassH03L 007/06AbstractA phase-locked loop circuit and method for providing for compensation for an offset. A phase-locked loop circuit comprises a phase detector, a compensation circuit, a loop filter, and a VCO. The phase detector is coupled to receive a first input signal and a second input signal. The phase detector is configured to output one or more of a plurality of output signals indicative of a difference between the first input signal and the second input signal. The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals. The compensation circuit is further configured to provide a plurality of compensated output signals. The loop filter is coupled to receive the compensated control signals. The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal. A method of operating a phase-locked loop circuit comprises receiving and comparing a first input signal and a second input signal and providing output signals indicative of the comparison. The method compensates for a voltage offset between the output signals and provides compensated output signals indicative of the compensation. The method filters the compensated control signals and provides a control signal indicative of the filtration. The method provides the second input signal based on the first control signal. Lower skew between the input and output may be achieved. | |
