Clocked pass transistor and complementary pass transistor logic circuits

Patent 6462582 Issued on October 8, 2002. Estimated Expiration Date:

June 12, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Time multiplexed ratioed logic
Patent #: 5612638
Issued on: 03/18/1997
Inventor: Lev

Dynamic logic circuits using transistors having differing threshold voltages
Patent #: 5831451
Issued on: 11/03/1998
Inventor: Bosshart

Semiconductor integrated circuit apparatus
Patent #: 5841300
Issued on: 11/24/1998
Inventor: Murabayashi, et al.

Dynamic logic circuit Patent #: 6060910
Issued on: 05/09/2000
Inventor: Inui

Inventor

Forbes, Leonard

Application

No. 878432 filed on 06/12/2001

US Classes:

326/98, MOSFET326/17, ACCELERATING SWITCHING326/95, Field-effect transistor326/113, Pass transistor logic or transmission gate logic327/208, Including field-effect transistor327/214, Complementary transistors327/224With single semiconductor device

Examiners

Primary: Tokar, Michael
Assistant: Tan, Vibol

Attorney, Agent or Firm

Dickstein Shapiro Morin & Oshinsky LLP

International Class

H03K 019/01

Abstract

A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.

Other References

L.A. Glasser and D.W. Dobberpuhl, "The Design and Analysis of VLSI circuits," Addison-Wesley, Reading Massachusetts, 1985, pp. 16-20
J.M. Rabaey, "Digital Integrated Circuits; A design perspective," Prentice Hall, Upper Saddle River, N.J., pp. 210-222, 1996
K. Bernstein et al., "High-speed Design Styles Leverage IBM Technology Prowess," MicroNews, vol. 4, No. 3, 1998
T. Fuse et al., "A 0.5V 200mhz 1-stage 32b ALU Using Bias Controlled SOI Pass-Gate Logic," Dig. IEE Int. Solid-State Circuits Conf., San Francisco, pp. 286-287, 1997
K. Yano et al., "Top-Down Pass-Transistor Logic Design," IEEE J. Solid-State Circuits, vol. 31, No. 6, pp. 792-803, Jun. 1996
K.H. Cheng et al., "A 1.2V CMOS Multiplier Using Low-Power Current Sensing Complementary Pass-Transistor Logic," Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, Oct., 13-16, vol. 2, pp. 1037-1040, 1996
S.I. Kayed et al., "CMOS Differential Pass-Transistor Logic (CMOS DPTL) Predischarge Buffer Design," 13th National Radio Science Conf., Cairo, Egypt, pp. 527-534, 1996
V.G. Oklobdzija, "Differential and Pass-Transistor CMOS Logic for High Performance Systems," Microelectronic J., vol. 29, No. 10, pp. 679-688, 1998
S. Yamashita et al., "Pass-Transistor?CMOS Collaborated Logic: The Best of Both Worlds," Dig. Symp. On VLSI Circuits, Kyoto, Japan, Jun., 12-14, pp. 31-32, 1997
R. Zimmerman et al., "Low-Power Logic Styles: CMOS Versus Pass Transistor Logic," IEEE J. Solid-State Circuits, vol. 32, No. 7, pp. 1079-1790, Jul. 1997
C. Tretz et al., "Performance Comparison of Differential Static CMOS Circuit Topologies in SOI Technology," Proc. IEEE Int. SOI Conference, Oct. 5-8, FL, pp. 123-124, 1998
L. McMurchie, S. Kio, G. Yee, T. Thorp, and C. Sechen, "Output Prediction Logic Techniques," Symp. on VLSI Circuits, Hawaii, Jun. 2000. (to be published