Enhanced embedded logic analyzer
June 21, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData acquisition system for capturing and storing clustered test data occurring before and after an event of interest Program control apparatus incorporating a trace function Flash EEPROM system which maintains individual memory block cycle counts Method and apparatus for making integrated circuits with built-in self-test On-chip in-circuit-emulator memory mapping and breakpoint register modules Method and apparatus for accessing internal integrated circuit signals Sample and load scheme for observability of internal nodes in a PLD Method and apparatus for monitoring or forcing an internal node in a programmable device Diagnostic interface system for programmable logic system development Emulation system with time-multiplexed interconnect InventorsApplicationNo. 887918 filed on 06/21/2001US Classes:714/39, Monitor recognizes sequence of events (e.g., protocol or logic state analyzer)703/16, Event-driven714/725, Programmable logic array (PLA) testing714/739Random pattern generation (includes pseudorandom pattern)ExaminersPrimary: Baderman, ScottAttorney, Agent or FirmForeign Patent References
International ClassG06F 011/25AbstractEmbedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.Other References
Field of SearchMonitor recognizes sequence of events (e.g., protocol or logic state analyzer)Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping) Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path) Programmable logic array (PLA) testing Built-in testing circuit (BILBO) Structural (in-circuit test) Including logic Event-driven Event-driven In-circuit emulator (i.e., ICE) Having details of setting or programming of interconnections or logic functions Array (e.g., PLA, PAL, PLD, etc.) | |
