Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout
Patent 6453457 Issued on September 17, 2002. Estimated Expiration Date: September 29, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Techniques for fabricating a device include forming a fabrication layout such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to a design layer. An evaluation point is determined for the edge based on a profile of amplitudes output from a proximity effects model along a transect. The transect includes a target edge in the design layer corresponding to the edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point. In other techniques, a dissection length parameter is derived based on a profile of amplitudes output by a proximity effects model along a transect. The transect includes a second edge in a second layout. An evaluation point is determined for a first edge based on the dissection length parameter. Then it is determined how to correct at least a portion of the first edge based on an analysis at the evaluation point.
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