Structure for folded architecture pillar memory cell
June 28, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDynamic random access memory device having a plurality of one-transistor type memory cells Dynamic ram cell with isolated trench capacitors Method of manufacturing dynamic RAM Bit line configuration for semiconductor memory Forming a bit line configuration for semiconductor memory High performance composed pillar DRAM cell Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors Method of making cross point four square folded bitline trench DRAM cell Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode Patent #: 5804852 Inventors
ApplicationNo. 604901 filed on 06/28/2000US Classes:438/272, Totally embedded in semiconductive layers257/302, Vertical transistor257/330, Gate electrode in groove257/E21.693, For vertical channel (EPO)257/E27.086, Storage electrode stacked over the transistor257/E27.091, Transistor in trench (EPO)257/E27.096, Vertical transistor (EPO)257/E27.097, Peripheral structure (EPO)257/E27.103, Electrically programmable ROM (EPO)438/270, Gate electrode in trench or recess in semiconductor substrate438/294Including isolation structureExaminersPrimary: Faumy, WaelAssistant: Berezny, Nema Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/336H01L 027/108 H01L 029/76 H01L 029/94 H01L 031/119 AbstractA densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.Field of SearchTotally embedded in semiconductive layersGate electrode in trench or recess in semiconductor substrate Vertical channel Plural gate electrodes (e.g., dual gate, etc.) Including isolation structure Including isolation structure Gate electrode in groove Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell) Gate electrode self-aligned with groove Vertical transistor Capacitor in trench | |
