Programmable line driver
Patent 6437599 Issued on August 20, 2002. Estimated Expiration Date: 
November 6, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 6, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOutput driver circuit with switched current source Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits Low voltage differential driver with multiple drive strengths High speed low voltage differential signal driver having reduced pulse width distortion Patent #: 6313662 InventorApplicationNo. 706904 filed on 11/06/2000US Classes:326/63, Logic level shifting (i.e., interface between devices of different logic families)326/30, Bus or line termination (e.g., clamping, impedance matching, etc.)326/82Current driving (e.g., fan in/out, off chip driving, etc.)ExaminersPrimary: Tokar, MichaelAssistant: Cho, James H. Attorney, Agent or FirmInternational ClassesH03K 019/017.5H03K 019/003 AbstractAn integrated circuit output driver has been described. The driver can operate in a mode selected from a group of possible modes. The described driver can operate in either a positive emitter coupled logic (PECL), a current mode logic (CML), a grounded low voltage differential signal (GLVDS), or a low voltage differential signal (LVDS) mode. The driver circuit includes a output driver, an emphasis circuit and termination circuitry. A driver bias circuit controls the bias currents for the output driver and the emphasis circuit. The driver bias circuit is controlled to select the desire driver mode. A termination circuitry can be activated based upon the selected mode.Field of SearchBus or line termination (e.g., clamping, impedance matching, etc.)Logic level shifting (i.e., interface between devices of different logic families) Field-effect transistor (e.g., JFET, MOSFET, etc.) ECL to/from GaAs FET (e.g., MESFET, etc.) ECL to/from MOS Supply voltage level shifting (i.e., interface between devices of a same logic family with different operating voltage levels) CMOS Current driving (e.g., fan in/out, off chip driving, etc.) Field-effect transistor Bus driving Having plural output pull-up or pull-down transistors | |
