Method and structure for creating high density buried contact for use with SOI processes for high performance logic
March 16, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for forming sloped topography contact areas between polycrystalline silicon and single-crystal silicon Buried interconnect for silicon on insulator structure Integrated circuit in silicon on insulator technology comprising a field effect transistor Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors Method of forming a transistor having an offset channel section SOI DRAM with field-shield isolation and body contact SOI DRAM with field-shield isolation Semiconductor device having SOI structure and manufacturing method therefor Method of making silicon on insulator buried plate trench capacitor Body contacted SOI MOSFET InventorsApplicationNo. 809888 filed on 03/16/2001US Classes:438/151, Having insulated gate257/E21.415, Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)257/E21.538, Making of internal connections, substrate contacts (EPO)257/E21.703, Substrate is semiconductor body (EPO)257/E27.112, Including insulator on semiconductor, e.g. SOI (silicon on insulator) (EPO)257/E29.275, With multiple gates (EPO)438/155, And additional electrical device on insulating substrate or layer438/249Doping by outdiffusion from a dopant source layer (e.g., doped oxide, etc.)ExaminersPrimary: Nelms, David C.Assistant: Tran, Mai-Huong Attorney, Agent or FirmInternational ClassH01L 021/00AbstractA semiconductor device having an SOI FET comprising a silicon body on an insulating layer on a conductive substrate. A gate dielectric and a gate are provided on a surface of the silicon body, and a source and a drain are provided on two sides of the gate. A buried body contact to the substrate conductor is provided below a third side of the gate. The buried body contact does not extend to the top surface of the silicon body. The body contact is separated from the gate by a second dielectric having a thickness typically greater than that of the gate dielectric. The body contact is a plug of conductive material, and the second dielectric coats the body contact under the gate. The FET can be used in an SRAM circuit or other type of circuit having a silicon-on-insulator (SOI) construction.Field of SearchHaving insulated gateAnd additional electrical device on insulating substrate or layer Doping by outdiffusion from a dopant source layer (e.g., doped oxide, etc.) Plural doping steps Using same conductivity-type dopant Including dielectric isolation means Full dielectric isolation with polycrystalline semiconductor substrate With electrical isolation means | |
