Data processing unit with interface for sharing registers by a processor and a coprocessor
November 9, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInterface between a microprocessor and a coprocessor Data processing system with coprocessor Microprocessor operable under direct connection to coprocessor Coprocessor instruction format Host processor which includes apparatus for performing coprocessor functions System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy Method for powering down a microprocessor embedded within a gate array Sharing of register stack by two execution units in a central processor Microcomputer having ALU performing min and max operations InventorsApplicationNo. 189111 filed on 11/09/1998US Classes:712/34, Including coprocessor712/23, Superscalar712/28, Distributed processing system712/32, Microprocessor or multichip or multimodule processor having sequential program control712/200, ARCHITECTURE BASED INSTRUCTION PROCESSING712/217Scoreboarding, reservation station, or aliasingExaminersPrimary: Maung, ZarniAssistant: El-Hady, Nabil Attorney, Agent or FirmForeign Patent References
International ClassG06F 015/00AbstractAn apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.Other References
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