Carry lookahead for programmable logic array
April 17, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable logic array having local and long distance conductors Look up table implementation of fast carry for adders and counters Logic structure and circuit for fast carry Fast carry structure with synchronous input Method and structure for providing fast propagation of a carry signal in a field programmable gate array Programmable logic array integrated circuit devices with flexible carry chains Programmable logic array integrated circuits with carry and/or cascade rings Fast carry-out scheme in a field programmable gate array FPGA having logic element carry chains capable of generating wide XOR functions Method and structure for providing fast conditional sum in a field programmable gate array InventorApplicationNo. 550919 filed on 04/17/2000US Classes:326/41, Significant integrated structure, layout, or layout interconnections326/38, Having details of setting or programming of interconnections or logic functions326/39Array (e.g., PLA, PAL, PLD, etc.)ExaminersPrimary: Tokar, MichaelAssistant: Tran, Andrew Q. Attorney, Agent or FirmForeign Patent References
International ClassH01L 025/00AbstractCarry lookahead techniques are adapted for implementation in a programmable logic device. In one example of the invention, a carry result is computed for a block of function cells, each function cell representing one bit in a multibit operation that uses carry. This carry result is combined with the carry input from a function cell block representing less significant bits in the operation and a carry output is provided to a function cell block representing more significant bits in the operation. The received carry can also be supplied to adjust provisional carry results for each bit associated with the function cells in the block. Accordingly, the received carry input need not be rippled through all the function cells in the block, thus reducing carry propagation delays. This technique is suitable for use in programmable logic devices because only minimal additional logic need be included in each block of function cells (such as the CLBs and LABs in the prior art), and because few, in any, new interconnections between blocks need be introduced.Other References
| |
