Flash memory with ultra thin vertical body transistors
February 9, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHigh density flash memory Ultra high density flash memory having vertically stacked devices Ultra high density flash memory Programmable memory address decode array with vertical transistors Four F2 folded bit line DRAM cell structure having buried bit and word lines Field programmable logic arrays with vertical transistors High density flash memory Memory cell having a vertical transistor with buried source/drain and dual gates Method of forming a logic array for a decoder Method for forming high density flash memory Patent #: 6238976 InventorsApplicationNo. 780169 filed on 02/09/2001US Classes:257/315, With floating gate electrode257/353, Single crystal islands of semiconductor layer containing only one active device257/E29.129, Gate electrodes for transistors with floating gate (EPO)257/E29.302Hi-lo programming levels only (EPO)ExaminersPrimary: Weiss, HowardAttorney, Agent or FirmInternational ClassesH01L 029/788H01L 027/01 H01L 027/12 H01L 031/039.2 AbstractStructures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a second contact layer vertically separated by an oxide layer. A single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical body region which separates an ultra thin single crystalline vertical first source/drain region and an ultra thin single crystalline vertical second source/drain region. A floating gate opposes the ultra thin single crystalline vertical body region, and a control gate separated from the floating gate by an insulator layer.Other References
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