Copper interconnect seed layer treatment methods and apparatuses for treating the same

Patent 6423200 Issued on July 23, 2002. Estimated Expiration Date:

September 30, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

3725224

Electrochemical planarization
Patent #: 5256565
Issued on: 10/26/1993
Inventor: Bernhardt, et al.

Plating device for wafer
Patent #: 5429733
Issued on: 07/04/1995
Inventor: Ishida

Method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate
Patent #: 5882498
Issued on: 03/16/1999
Inventor: Dubin, et al.

Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers
Patent #: 6001730
Issued on: 12/14/1999
Inventor: Farkas, et al.

Polishing composition including an inhibitor of tungsten etching
Patent #: 6083419
Issued on: 07/04/2000
Inventor: Grumbine, et al.

Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece Patent #: 6197181
Issued on: 03/06/2001
Inventor: Chen

Inventor

Hymes, Diane J.

Assignee

Lam Research Corporation

Application

No. 410110 filed on 09/30/1999

US Classes:

205/123, Product is semiconductor or includes semiconductor205/183, Forming nonelectrolytic coating before depositing predominantly single metal or alloy electrolytic coating205/205, Treating substrate prior to coating257/E21.584, Barrier, adhesion or liner layer (EPO)257/E21.585Filling of holes, grooves, vias or trenches with conductive material (EPO)

Examiners

Primary: Valentine, Donald R.
Assistant: Smith-Hicks, Erica

Attorney, Agent or Firm

Martine & Penilla, LLP

Foreign Patent References

0 880 168 EP. 11/19/1998
0 903 774 EP. 03/19/1999
11335896 JP. 07/19/1999
WO 99/09593 WO. 02/19/1999
WO 99/47731 WO. 09/19/1999

International Classes

C25D 005/02
C25D 005/34
C25C 028/00

Abstract

A method for making semiconductor interconnect features in a dielectric layer is provided. The method includes depositing a copper seed layer over a barrier layer that is formed over the dielectric layer and into etched features of the dielectric layer. The copper seed layer is then treated to remove an oxidized layer from over the copper seed layer. The method then moves to electroplating a copper fill layer over the treated copper seed layer. The copper fill layer is configured to fill the etched features of the dielectric layer.