U.S. patents available from 1976 to present.
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Jig used for assembling semiconductor devices

Patent 6423102 Issued on July 23, 2002. Estimated Expiration Date: Icon_subject December 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Distortion free 3 point vacuum fixture
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Self-compensating hydrostatic flattening of semiconductor substrates
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Packaging system for multiple semiconductor devices
Patent #: 4763188
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Etching apparatus
Patent #: 4968375
Issued on: 11/06/1990
Inventor: Sato, et al.

Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
Patent #: 5034350
Issued on: 07/23/1991
Inventor: Marchisi

Method for fabricating a multichip semiconductor device having two interdigitated leadframes
Patent #: 5147815
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Semiconductor device package and method of making such a package
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Inventors

Application

No. 987054 filed on 12/09/1997

US Classes:

29/25.01, BARRIER LAYER OR SEMICONDUCTOR DEVICE MAKING269/21, Vacuum-type holding means277/910O-RING SEAL

Examiners

Primary: Graybill, David E.

Foreign Patent References

  • 4026244 EP. 02/11/1992
  • 58110048 JP. 06/11/1983
  • 58142537 JP. 08/11/1983
  • 6191936 JP. 05/11/1986
  • 62219531 JP. 09/11/1987
  • 1218032 JP. 08/11/1989
  • 5121462 JP. 05/11/1993

International Classes

H01L 021/00
H01L 021/64
B25B 011/00

Foreign Application Priority Data

1994-11-30 JP

Abstract

A jig used for assembling semiconductor devices has an arrangement wherein the first semiconductor integrated circuit chip, which is die-bonded and wire-bonded onto one surface of a lead frame, is fitted to the inner section of a support stage and is supported by an elastic member that is designed to be higher than the inner section, while the lead frame is supported by the outer section of the support stage. In this state, the second semiconductor integrated circuit chip is die-bonded onto the other surface of the lead frame by applying pressure by means of a bonding collet. Thus, it becomes possible to prevent cracks that may be caused in a passivation film and also to improve the reliability and the final yield of semiconductor devices.

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