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US Patent 6423102 - Jig used for assembling semiconductor devices
US Patent Issued on July 23, 2002
Estimated Patent Expiration Date:
December 9, 2017Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
December 9, 2017Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA jig used for assembling semiconductor devices has an arrangement wherein the first semiconductor integrated circuit chip, which is die-bonded and wire-bonded onto one surface of a lead frame, is fitted to the inner section of a support stage and is supported by an elastic member that is designed to be higher than the inner section, while the lead frame is supported by the outer section of the support stage. In this state, the second semiconductor integrated circuit chip is die-bonded onto the other surface of the lead frame by applying pressure by means of a bonding collet. Thus, it becomes possible to prevent cracks that may be caused in a passivation film and also to improve the reliability and the final yield of semiconductor devices. | InventorsApplicationNo. 987054 filed on 12/09/1997US Classes:29/25.01, BARRIER LAYER OR SEMICONDUCTOR DEVICE MAKING269/21, Vacuum-type holding means277/910O-RING SEALField of Search29/25.01, BARRIER LAYER OR SEMICONDUCTOR DEVICE MAKING269/21, Vacuum-type holding means277/910O-RING SEALExaminersPrimary: Graybill, David E.US Patent References2730370, 4357006, Distortion free 3 point vacuum fixtureIssued on: 11/02/1982 Inventor: Hayes4470856, Self-compensating hydrostatic flattening of semiconductor substrates Issued on: 09/11/1984 Inventor: Little , et al.4763188, Packaging system for multiple semiconductor devices Issued on: 08/09/1988 Inventor: Johnson4795518, Method using a multiple device vacuum chuck for an automatic microelectronic bonding apparatus Issued on: 01/03/1989 Inventor: Meinel , et al.4949783, Substrate transport and cooling apparatus and method for same Issued on: 08/21/1990 Inventor: Lakios, et al.4968375, Etching apparatus Issued on: 11/06/1990 Inventor: Sato, et al.5034350, Semiconductor device package with dies mounted on both sides of the central pad of a metal frame Issued on: 07/23/1991 Inventor: Marchisi5147815, Method for fabricating a multichip semiconductor device having two interdigitated leadframes Issued on: 09/15/1992 Inventor: Casto5173766, Semiconductor device package and method of making such a package Issued on: 12/22/1992 Inventor: Long, et al.5273938, Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film Issued on: 12/28/1993 Inventor: Lin, et al.5366933, Method for constructing a dual sided, wire bonded integrated circuit chip package Issued on: 11/22/1994 Inventor: Golwalkar, et al.5437777, Apparatus for forming a metal wiring pattern of semiconductor devices Issued on: 08/01/1995 Inventor: Kishi5527740, Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities Issued on: 06/18/1996 Inventor: Golwalkar, et al.5759873Method of manufacturing chip-size package-type semiconductor device Issued on: 06/02/1998 Inventor: Kata, et al. Foreign Patent References
International ClassesH01L 021/00H01L 021/64 B25B 011/00 Foreign Application Priority Data1994-11-30 JP |
