Method of programming and erasing non-volatile memory cells
January 3, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSingle transistor electrically programmable memory device and method Flash memory cell and its operation Method for bulk (or byte) charging and discharging an array of flash EEPROM memory cells Non-volatile semiconductor memory device and method for erasure and production thereof Drain excluded EPROM cell Self-convergence of post-erase threshold voltages in a flash memory cell using transient response Electron injection method for substrate-hot-electron program and erase VT tightening for ETOX cell Method of operating flash memory Patent #: 6366499 InventorsApplicationNo. 683463 filed on 01/03/2002US Classes:365/185.28, Tunnel programming257/E27.103, Electrically programmable ROM (EPO)257/E29.309, With charge trapping gate insulator (e.g., MNOS-memory transistors) (EPO)365/185.18Particular biasingExaminersPrimary: Nguyen, Tan T.Attorney, Agent or FirmInternational ClassG11C 016/00AbstractA method of selectively programming an individual memory cell of a non-volatile memory array. The non-volatile memory array is an array of memory cells. Each memory cell is made up of an ONO gate built on a substrate, which also acts as a well. On one side of the gate is a diffusion drain encompassed by a localized well region set in the well. On the other side of the gate is a diffusion source set in the well. When operated, appropriate voltages are applied to the source, the gate, the drain, and the localized well region to program or erase the non-volatile memory. The designed localized well region prevents an induction current in the unselected gates of the array, allowing for better selectivity and performance. | |
