Efficient and robust random access memory cell suitable for programmable logic configuration control
Patent 6418045 Issued on July 9, 2002. Estimated Expiration Date: 
June 28, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 28, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesEfficient and robust random access memory cell suitable for programmable logic configuration control Patent #: 6292388 InventorAssigneeApplicationNo. 896406 filed on 06/28/2001US Classes:365/156, Complementary365/154Flip-flop (electrical)ExaminersPrimary: Nelms, David C.Assistant: Tran, M. Attorney, Agent or FirmInternational ClassG11C 011/00AbstractFor a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation comprises steps of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak passgate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches. A memory cell with such a weak passgate and operating characteristics is taught, a configuration memory using such cells, and a Programmable Logic Array with such a configuration memory.Other References
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