U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Multiprocessor system with a high performance integrated distributed switch (IDS) controller

Patent 6415424 Issued on July 2, 2002. Estimated Expiration Date: Icon_subject November 9, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Switch matrix having integrated crosspoint logic and method of operation
Patent #: 5226125
Issued on: 07/06/1993
Inventor: Balmer, et al.

Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
Patent #: 5359536
Issued on: 10/25/1994
Inventor: Agrawal, et al.

Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
Patent #: 5644496
Issued on: 07/01/1997
Inventor: Agrawal, et al.

Symmetric multiprocessing computer with non-uniform memory access architecture
Patent #: 5887146
Issued on: 03/23/1999
Inventor: Baxter, et al.

Data processing system and method for implementing a switch protocol in a communication system
Patent #: 5949982
Issued on: 09/07/1999
Inventor: Frankeny, et al.

System and method of memory access in apparatus having plural processors and plural memories Patent #: 6070003
Issued on: 05/30/2000
Inventor: Gove, et al.

Inventors

Application

No. 437195 filed on 11/09/1999

US Classes:

716/8, Floorplanning710/317, Crossbar712/38, Offchip interface716/12Routing (e.g., routing map, netlisting)

Examiners

Primary: Smith, Matthew
Assistant: Kik, Phallaka

Attorney, Agent or Firm

International Classes

G06F 017/50
G06F 013/40
G06F 015/173

Abstract

A data processing system having a modified processor chip and external components to the processor chip. The processor chip is interconnected to the external components via point-to-point bus connections controlled by an integrated distributed switch (IDS) controller. The IDS controller is placed, during chip design, in the upper layer metals of the processor chip. When the data processing system is a multi-chip multiprocessor data processing system, the IDS controller operates to provide a pseudo switching effect whereby the processor is directly connected to each external component. The IDS controller permits the processor to have greater communication bandwidth and reduced latencies with the external components. It also allows for a connection to distributed external components such as memory and I/O, etc. with overall reduced system components.

Other References

  • Savari ("Capability analysis of distributed switching systems in interprocessor communications", Proceedings of TRICOMM '91, IEEE Conference on Communications Software: Communications for Distributed Applications and Systems, Apr. 18, 1991, pp. 243-256
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