Patent ReferencesMemory cell having a super supply voltage Semiconductor device incorporating voltage reduction circuit therein Patent #: 5463585 InventorsApplicationNo. 681989 filed on 07/03/2001US Classes:365/201TestingExaminersPrimary: Zarabian, A.Attorney, Agent or FirmInternational ClassG11C 007/00AbstractA apparatus uses a test method to perform burn-in testing of a static random access memory that has a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, and a plurality of memory cells for storing data. Each of the memory cells is coupled to a corresponding word line, a corresponding first bit line, a corresponding second bit line, and a power supply that is used to apply a working voltage to the memory cell to drive the memory cell. When the apparatus tests the static random access memory, the apparatus adjusts the working voltage according to a potential of the word lines and voltage gaps between the first bit lines and the second bit lines. | |