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AbstractA apparatus uses a test method to perform burn-in testing of a static random access memory that has a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, and a plurality of memory cells for storing data. Each of the memory cells is coupled to a corresponding word line, a corresponding first bit line, a corresponding second bit line, and a power supply that is used to apply a working voltage to the memory cell to drive the memory cell. When the apparatus tests the static random access memory, the apparatus adjusts the working voltage according to a potential of the word lines and voltage gaps between the first bit lines and the second bit lines. | InventorsApplicationNo. 681989 filed on 07/03/2001US Classes:365/201TestingField of Search365/201, Testing365/189.11, Including level shift or pull-up circuit365/226, POWERING365/207Differential sensingExaminersPrimary: Zarabian, A.Attorney, Agent or FirmUS Patent References5379260, Memory cell having a super supply voltageIssued on: 01/03/1995 Inventor: McClure5463585Semiconductor device incorporating voltage reduction circuit therein Issued on: 10/31/1995 Inventor: Sanada International ClassG11C 007/00 |