Abstract

Systems and methods are provided for double pass transistor logic with vertical gate transistors. The vertical gate transistors have multiple vertical gates which are edge defined such that only a single transistor is required for multiple logic inputs. Thus, a minimal surface area is required for each logic input. In one embodiment, a novel integrated circuits described in the present invention includes a number of input lines for receiving input signals and at least one output line for providing output signals. One or more arrays of transistors are coupled between the number of input lines and the at least one output line. Each transistor includes source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. Further at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. The number of vertical gates each have a horizontal width which has sub-lithographic dimensions. In the invention, the number of vertical gates are independently coupled to a number of gate input lines. Thus, the number of vertical gates provide logic inputs such that a minimal area in each logic cell is used for each logic input. Other integrated circuits using the present invention are similarly provided.