In-service programmable logic arrays with ultra thin vertical body transistors
February 9, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesTechnique for producing small islands of silicon on insulator High density flash memory Ultra high density flash memory Programmable memory address decode array with vertical transistors Four F2 folded bit line DRAM cell structure having buried bit and word lines Field programmable logic arrays with vertical transistors Memory cell having a vertical transistor with buried source/drain and dual gates Method of forming a logic array for a decoder Programmable logic array with vertical transistors Method for forming high density flash memory Patent #: 6238976 InventorApplicationNo. 780129 filed on 02/09/2001US Classes:326/41, Significant integrated structure, layout, or layout interconnections257/E21.693, For vertical channel (EPO)257/E27.103, Electrically programmable ROM (EPO)326/101, SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS326/102Field-effect transistorExaminersPrimary: Tokar, MichaelAssistant: Tran, Andrew Q. Attorney, Agent or FirmInternational ClassH01L 025/00AbstractStructures and methods for in-service programmable logic arrays with ultra thin vertical body transistors are provided. The in-service programmable logic array includes a first logic plane that receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in-service programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. At least one single crystalline ultra thin vertical floating gate transistor that is disposed adjacent each vertical pillar. The single crystalline vertical floating gate transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A vertical floating gate opposes the ultra thin single crystalline vertical body region.Other References
Field of SearchHaving details of setting or programming of interconnections or logic functionsArray (e.g., PLA, PAL, PLD, etc.) Significant integrated structure, layout, or layout interconnections Field effect transistor Complementary FET`s Significant integrated structure, layout, or layout interconnections Field-effect transistor Field-effect transistor Complementary FET`s SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS | |
