Method and apparatus for injection molded flip chip encapsulation
January 12, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor device insulation method Lead frame assembly for an integrated circuit molding system Flip-chip package for integrated circuits Electrical component package comprising polymer-reinforced solder bump interconnection Connecting of semiconductor chips to circuit substrates Vacuum infiltration of underfill material for flip-chip devices Semiconductor device with controlled spread polymeric underfill Overmolded semiconductor device having solder ball and edge lead connective structure Flip chip encapsulating compositions and semiconductor devices encapsulated therewith Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film InventorsApplicationNo. 228601 filed on 01/12/1999US Classes:257/778, Flip chip257/738, Ball shaped257/787, ENCAPSULATED257/E21.501, Providing fillings in container, e.g., gas fillings (EPO)257/E21.503, Encapsulation of active face of flip chip device, e.g., under filling or under encapsulation of flip-chip, encapsulation perform on chip or mounting substrate (EPO)257/E23.125, Substrate forming part of encapsulation (EPO)257/E23.126Double encapsulation or coating and encapsulation (EPO)ExaminersPrimary: Lee, EddieAssistant: Cruz, Lourdes Attorney, Agent or FirmForeign Patent References
International ClassH01L 023/48AbstractThe electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.Other References
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