Method to control mechanical stress of copper interconnect line using post-plating copper anneal
May 4, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesEliminating metal extrusions by controlling the liner deposition temperature Method for forming multileves interconnections for semiconductor fabrication Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper Sputter deposition and annealing of copper alloy metallization Interconnect structure using Al2 Cu for an integrated circuit chip Site-selective electrochemical deposition of copper Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with copper Method for manufacturing a semiconductor device Storage-annealing plated CU interconnects Method of forming diffusion barriers for copper metallization in integrated cirucits Patent #: 6245672 InventorAssigneeApplicationNo. 564610 filed on 05/04/2000US Classes:438/687, Copper of copper alloy conductor257/E21.577, By forming via holes (EPO)257/E21.579, For "dual damascene" type structures (EPO)257/E21.582, Characterized by formation and post treatment of conductors, e.g., patterning (EPO)257/E21.585, Filling of holes, grooves, vias or trenches with conductive material (EPO)438/625, At least one metallization level formed of diverse conductive layers438/626, Planarization438/630, Silicide formation438/648, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/653At least one layer forms a diffusion barrierExaminersPrimary: Smith, MatthewAssistant: Yevsikov, V. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/44AbstractA method is provided, the method comprising forming a first dielectric layer above a first structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure above the first dielectric layer and in the first opening. The method also comprises annealing the first copper structure using one of a furnace anneal process performed at a temperature ranging from approximately 100-400° C. for a time ranging from approximately 10-90 minutes and a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 100-400° C. for a time ranging from approximately 10-180 seconds.Field of SearchCopper of copper alloy conductorAt least one metallization level formed of diverse conductive layers At least one layer forms a diffusion barrier Planarization Silicide formation Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof) With formation of opening (i.e., viahole) in insulative layer Utilizing reflow Combined with formation of ohmic contact to semiconductor region Having adhesion promoting layer Refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof) Silicide | |
