Patent ReferencesHigh resolution patterning on solid substrates Device analysis for face down chip Method and apparatus for monitoring wafer characteristics and/or semiconductor processing consistency using wafer charge distribution measurements Check abnormal contact and via holes by electroplating method Patent #: 6261852 InventorsAssigneeApplicationNo. 921121 filed on 08/02/2001US Classes:438/14, WITH MEASURING OR TESTING257/E21.527, Optical enhancement of defects or not directly visible states, e.g., selective electrolytic deposition, bubbles in liquids, light emission, color change (EPO)438/9, Plasma etching438/15, Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor438/16, Optical characteristic sensed438/17Electrical characteristic sensedExaminersPrimary: Niebling, John F.Assistant: Luk, Olivia Attorney, Agent or FirmInternational ClassH01L 021/66Foreign Application Priority Data2001-01-24 DEAbstractFor determining the quality of an opening formed in a dielectric material layer, a voltage contrast inspection tool is used to produce a voltage contrast image of a test pattern formed in the dielectric material layer. The voltage contrast values of openings may be compared to a reference contrast value or to different openings so as to decide whether or not the opening has a required depth. | |