Decoder for memories having optimized configuration
Patent 6362658 Issued on March 26, 2002. Estimated Expiration Date: 
November 20, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 20, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDigital multiplexer circuit Logic circuit High performance dynamic multiplexers without clocked NFET MOS logic circuit and semiconductor apparatus including the same Vertical gate transistors in pass transistor logic decode circuits Patent #: 6222788 InventorApplicationNo. 716747 filed on 11/20/2000US Classes:326/105, Decoding326/106, With field-effect transistor326/108, CMOS365/230.06Particular decoder or driver circuitExaminersPrimary: Tokar, MichaelAssistant: Tan, Vibol Attorney, Agent or FirmInternational ClassH03K 019/084Foreign Application Priority Data1999-11-25 ITAbstractA decoder with reduced complexity includes at least one OR circuit section and at least one AND circuit section. The at least one OR circuit section may include first and second circuit lines mutually connected and respectively receiving as inputs an address signal and an inverted address signal. The at least one AND circuit section may include first and second circuit lines which respectively receive as inputs the inverted address signal and the address signal. The at least one OR circuit section and the at least one AND circuit section may be connected to first and second booster circuits. Furthermore, the at least one OR circuit section may also include a virtual ground. | |
