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Analog to digital converter having a digital to analog converter mode

Patent 6359575 Issued on March 19, 2002. Estimated Expiration Date: Icon_subject December 9, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Signal conditioning circuit including a combined ADC/DAC, sensor system, and method therefor
Patent #: 5995033
Issued on: 11/30/1999
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System and method for reducing errors in an analog to digital converter
Patent #: 6016112
Issued on: 01/18/2000
Inventor: Knudsen

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Patent #: 6020838
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System and method for generating a linearity error correction device for an analog to digital converter Patent #: 6049298
Issued on: 04/11/2000
Inventor: Knudsen

Inventor

Assignee

Application

No. 458539 filed on 12/09/1999

US Classes:

341/118, CONVERTER COMPENSATION341/120CONVERTER CALIBRATION OR TESTING

Examiners

Primary: Wamsley, Patrick

Attorney, Agent or Firm

International Classes

H03M 001/10
H03M 001/06

Abstract

An analog to digital (A/D) converter which includes A/D converter and D/A converter modes. The A/D converter includes an internal digital to analog (D/A) converter (DAC) that may be used in a feedback loop during A/D operations (in the A/D mode), and may be used as a stand-alone D/A converter in the D/A mode. The present invention also takes advantage of advanced calibration techniques available for the internal D/A converter of the A/D converter. A processing unit may be coupled to the output of the internal A/D converter. The processing unit or a separate computer system may perform a calibration function in the A/D mode to generate linearity error correction information for correcting linearity errors in the internal D/A converter. The linearity error correction information may be used in configuring a linearity error correction device implemented by the processing unit. In the A/D mode, the processing unit may implement linearity error correction and a decimation function during A/D conversion. In the D/A mode, the processing unit also may implement linearity error correction functions as well as other functions during D/A conversion. The A/D converter may also include switching elements used in configuring the A/D converter in either the A/D mode or the D/A mode.

Other References

  • Delta-Sigma Data Converters, IEEE Press, 1997, Chapter pp. 244-28
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