Method and system for low level testing of central electronics complex hardware using Test nano Kernel
February 1, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for testing a digital computer Architecture and method for testing VLSI processors Service processor tester Memory testing with preservation of in-use data Computer program debugging system and method Method and apparatus to emulate VLSI circuits within a logic simulator System for constructing hardware device interface software systems independent of operating systems including capability of installing and removing interrupt handlers Decoding guest instruction to directly access emulation routines that emulate the guest instructions Processor with sequences of processor instructions for locked memory updates System and method for verifying processor performance InventorsApplicationNo. 241108 filed on 02/01/1999US Classes:714/39, Monitor recognizes sequence of events (e.g., protocol or logic state analyzer)714/25Fault locating (i.e., diagnosis or testing)ExaminersPrimary: Ray, Gopal C.Attorney, Agent or FirmInternational ClassesG06F 011/00G06F 011/22 AbstractThe method and system of the present invention provides for a test tool consisting of a Test nano Kernel and supported test programs (exercisers) which sequentially stage validity tests for central complex electronics hardware for architecture and hardware implementation for a single processor or in a multiprocessor system. Central electronics complex hardware is a processor, memory sub-system and system bridge coupled together and may include the input/output ports. Each stage becomes increasingly complex as the hardware platform becomes more stable. The Test nano Kernel consists of approximately 500 K of software code, provides multiprocessor support and implements context and 64-bit execution, effective equal to real and shared memory service, segment register attachment, gang scheduling and CPU affinity services. The Test nano Kernel provides for a smooth transition from simulation due to its capabilities to run simulation test cases on real hardware.Field of SearchFor reliability enhancing component (e.g., testing backup spare, or fault injection)Memory or storage device component fault Particular stimulus creation Monitor recognizes sequence of events (e.g., protocol or logic state analyzer) Fault locating (i.e., diagnosis or testing) Device response compared to expected fault-free response Substituted emulative component (e.g., emulator microprocessor) Derived from analysis (e.g., of a specification or by stimulation) Circuit simulation Including logic Computer or peripheral device Bridge between bus systems | |
