Wide shifting in the vector permute unit
May 17, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDigital companding circuit Barrel shifter circuit having rotation function Bidirectional shifter Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode Cache burst architecture for parallel processing, such as for image processing Shifter for shifting floating point number utilizing arithmetic operation of redundant binary number, and adder containing the same Fast conversion two's complement encoded shift value for a barrel shifter Data processing system and method of permutation with replication within a vector register file Fast shift amount decode for VMX shift and vperm instructions Vector packing and saturation detection in the vector permute unit Patent #: 6178500 Inventors
ApplicationNo. 572058 filed on 05/17/2000US Classes:710/317, Crossbar708/209, Shifting712/2Vector processorExaminersPrimary: Dharia, RupalAttorney, Agent or FirmInternational ClassesG06F 013/00G06F 013/38 AbstractA crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.Field of SearchPROCESSING ARCHITECTUREVector processor Scalar/vector processor interface Distributing of vector data to vector registers Masking to control an access to data in vector register Controlling access to external vector data Vector processor operation Multimode (e.g., MIMD to SIMD, etc.) Multiple instruction, Multiple data (MIMD) Single instruction, multiple data (SIMD) Superscalar Long instruction word Shifting | |
