Semiconductor device and manufacturing method thereof
June 18, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of fabricating self-aligned silicon-on-insulator like devices Integrated circuit structure with active device in merged slot and method of making same Method of manufacture a primos device Semiconductor device Method of fabricating complementary poly emitter transistors Elevated-gate field effect transistor structure and fabrication method Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain Transistor with ultra shallow tip and method of fabrication Semiconductor device and manufacturing method thereof Method of forming a transistor InventorsApplicationNo. 098736 filed on 06/18/1998US Classes:438/300, Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)257/E21.106, Doping during the epitaxial deposition (EPO)257/E21.131, Selective epilaxial growth, e.g., simultaneous deposition of mono- and non-mono semiconductor material (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)257/E29.116, Source or drain electrodes for field-effect devices (EPO)257/E29.117, For thin film transistors with insulated gate (EPO)257/E29.146, On silicon (EPO)257/E29.147, For thin-film silicon (EPO)257/E29.277, Characterized by drain or source properties (EPO)438/199, Complementary insulated gate field effect transistors (i.e., CMOS)438/279, Making plural insulated gate field effect transistors having common active region438/299, Self-aligned438/303Utilizing gate sidewall structureExaminersPrimary: Pham, LongAssistant: Hawranek, Scott J. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 027/108H01L 029/76 H01L 029/94 H01L 031/119 Foreign Application Priority Data1994-09-13 JPAbstractA method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region. | |
