Semiconductor arithmetic circuit and data processing device
March 13, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesNeuron circuit One-transistor adaptable analog storage element and array Data synapse expressing unit capable of refreshing stored synapse load Semiconductor device Programmable logic circuit w/neuron MOS transistors Semiconductor devices utilizing neuron MOS transistors Source follower using NMOS and PMOS transistors Neuron circuit Semiconductor integrated data matching circuit Semiconductor neural circuit device InventorsAssigneeApplicationNo. 041531 filed on 03/13/1998US Classes:706/33, Semiconductor neural network326/98, MOSFET326/119, MOSFET (i.e., metal-oxide semiconductor field-effect transistor)327/389Insulated gate FET (e.g., MOSFET, etc.)ExaminersPrimary: Davis, George B.Attorney, Agent or FirmForeign Patent References
International ClassesG06F 015/18H03K 019/096 H03K 017/16 Foreign Application Priority Data1997-03-15 JPAbstractA semiconductor device capable of executing size comparison operations on a plurality of data at high speed and in real time and using simple circuitry. An inverter circuit group is used containing a plurality of inverter circuits constructed using neuron MOS transistors. Predetermined signal voltages are applied from the exterior to the first input gates of the inverter circuits, and the output signals of all inverters contained in the inverter circuit group are inputted into a first logical arithmetic circuit and a second logical arithmetic circuit, and the output signal of the first logical arithmetic circuit is inputted into a third logical arithmetic circuit controlled by the output signal of the second logical arithmetic circuit, and the output of the third logical arithmetic circuit is fed back to the second input gates of the inverter circuits contained in the inverter circuit group. Bye use of the output signals of the inverter circuit groups, the position having the maximum voltage among the signal voltages inputted into the inverter circuit groups is specified.Other References
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