Transistor with ultra shallow tip and method of fabrication
Patent 6326664 Issued on December 4, 2001. Estimated Expiration Date: 
November 17, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 17, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRaised source/drain transistor Method of fabricating a raised source/drain transistor Method of fabricating an high-performance insulated-gate field-effect transistor High electron mobility transistor Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures High-performance insulated-gate field-effect transistor Method of forming a SOI transistor having a self-aligned body contact Patent #: 5405795 InventorsApplicationNo. 971992 filed on 11/17/1997US Classes:257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/19, Si x Ge 1-x257/65, Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier)257/336, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/377, With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)257/382, With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)257/385, Multiple polysilicon layers257/742, With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal)257/755, Polysilicon laminated with silicide257/773, Of specified configuration257/E21.148, From or through or into an applied layer, e.g., photoresist, nitride (EPO)257/E21.151, Applied layer being silicon or silicide or SIPOS, e.g., polysilicon, porous silicon (EPO)257/E21.201, Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)257/E21.428, With a recessed gate, e.g., lateral U-MOS (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)257/E21.64, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)257/E29.122, Characterized by relative position of source or drain electrode and gate electrode (EPO)257/E29.143, Ohmic electrodes (EPO)257/E29.155, Multiple silicon layers257/E29.156, Including silicide layer contacting silicon layer (EPO)257/E29.267, With nonplanar structure (e.g., gate or source or drain being nonplanar) (EPO)438/62, Using running length substrate438/65, Having additional optical element (e.g., optical fiber, etc.)438/131, Using structure alterable to conductive state (i.e., antifuse)438/231, Plural doping steps438/272, Totally embedded in semiconductive layers438/277, Including forming overlapping gate electrodes438/278, After formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.)438/290, After formation of source or drain regions and gate electrode438/327, Having lateral bipolar transistor438/334Forming inverted transistor structureExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmForeign Patent References
International ClassesH01L 029/06H01L 021/265 AbstractA novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.Other References
Field of SearchSi x Ge 1-xNon-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier) With lightly doped portion of drain region adjacent channel (e.g., LDD structure) With lightly doped portion of drain region adjacent channel (e.g., LDD structure) With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide) With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide) Multiple polysilicon layers With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal) Polysilicon laminated with silicide Of specified configuration Using running length substrate Having additional optical element (e.g., optical fiber, etc.) Using structure alterable to conductive state (i.e., antifuse) Plural doping steps Totally embedded in semiconductive layers Including forming overlapping gate electrodes After formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.) After formation of source or drain regions and gate electrode Having lateral bipolar transistor Forming inverted transistor structure | |
