Application specific automated test equipment system for testing integrated circuit devices in a native environment
January 26, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPortable deployable automatic test system Testing set up and hold input timing parameters of high speed integrated circuit devices Per pin circuit test system having N-bit pin interface providing speed improvement with frequency multiplexing Method and apparatus for selectable parallel execution of test operations Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system Fault-tolerant hierarchical bus system and method of operating same Automated test equipment digital tester expansion apparatus VXIbus device which intelligently monitors bus conditions and begins early cycles for improved performance Low cost, highly parallel memory tester InventorAssigneeApplicationNo. 238649 filed on 01/26/1999US Classes:702/117, Of circuit702/108, TESTING SYSTEM702/109, For transfer function determination702/110, Binary signal stimulus (e.g., pulse)702/115Electromechanical or magnetic systemExaminersPrimary: Hoff, Marc S.Assistant: Tsai, Carol S. W. Attorney, Agent or FirmForeign Patent References
International ClassG01R 031/28AbstractAn application specific automated test equipment system for source synchronous bus interface devices is described. A native interface board is provided to interface an automated test unit and a device under test. The native interface board is configured with devices selected to recreate a native environment of the device under test. A first clock drives the devices on the native interface board. A second clock drives the device under test. The second clock signal is derived from the first clock signal to form a substitute clock signal that can be adjusted in relation to the first clock signal. Input and output timing relationships of the device under test are determined by altering the arrival time of the substitute clock at the device under test with respect to the timing of the first clock signal.Other References
Field of SearchIncluding specific communication meansOf mechanical system Timing signal MEASUREMENT SYSTEM Of circuit Testing multiple circuits Noise signal stimulus (e.g., white noise) Signal generation or waveform shaping Electromechanical or magnetic system Of sensing device Binary signal stimulus (e.g., pulse) Sinusoidal signal stimulus Signal conversion Pneumatic or hydraulic system For transfer function determination Including input/output or test mode selection means Including program set up Including program initialization (e.g., program loading) or code selection (e.g., program creation) TESTING SYSTEM Including multiple test instruments Clock or synchronization Scan path testing (e.g., level sensitive scan design (LSSD)) Of individual circuit component or element System sensing fields adjacent device under test (DUT) Internal of or on support for device under test (DUT) DUT including test circuit Bipolar transistor | |
