Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system
Method and apparatus for selecting instructions for simultaneous execution
Software invalidation in a multiple level, multiple cache system
Encrypting and decrypting instruction boundaries of instructions in a superscalar data processing system
Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel
Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction
Object-code compatible representation of very long instruction word programs
Method and apparatus for improved aligned/misaligned data load from cache
Method and system for load data formatting and improved method for cache line organization Patent #: 6085289
ApplicationNo. 205120 filed on 12/03/1998
US Classes:712/204, INSTRUCTION ALIGNMENT712/24, Long instruction word712/206Of multiple instructions simultaneously
ExaminersPrimary: Treat, William M.
Attorney, Agent or Firm
Foreign Patent References
International ClassG06F 009/00
AbstractThe present invention provides an efficient method for fetching instructions having a non-power of two size. In one embodiment, a method for fetching instructions having a non-power of two size includes fetching a first instruction cache line having a power of two size for storage in a first line buffer of an instruction fetch unit of a microprocessor, fetching a second instruction cache line having a power of two size for storage in a second line buffer of the instruction fetch unit, and extracting and aligning instruction data stored in the first line buffer and the second line buffer to provide an instruction having a non-power of two size.