Low-power memory system with incorporated vector processing
February 22, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements Cache memory with variable fetch and replacement schemes System and method for on-line state restoration of one or more processors in an N module redundant voting processor system Method and apparatus for refreshing a selected portion of a dynamic random access memory Cache-based computer system employing a snoop control circuit with write-back suppression Apparatus, systems and methods for improving data cache hit rates Cache array select logic allowing cache array size to differ from physical page size Videophone multimedia interactive on-hold information menus Reducing power consumption in computer memory Patent #: 6134167 InventorAssigneeApplicationNo. 255031 filed on 02/22/1999US Classes:713/320, Power conservation365/222, Data refresh711/106, Refresh scheduling711/133, Entry replacement strategy711/141, Coherency711/143, Write-back712/2, Vector processor712/207PrefetchingExaminersPrimary: Nguyen, Hiep T.Attorney, Agent or FirmForeign Patent References
International ClassG06F 001/26AbstractA battery-powered portable radio device saves on the overall power consumed by the whole device by skipping unnecessary read, write, and refresh cycles of the internal main memory DRAM core. Streaming data input from a radio receiver is analyzed by a vector processor. The DRAM main memory and the vector processor itself share real estate on a common semiconductor chip. This allows a very wide row of DRAM memory to communicate 1024 bits wide with an eight-line cache. Six lines of the cache are reserved for memory operations, and two lines are reversed for I/O operations. Streaming data from the radio receiver is stored up in the DRAM main memory via the two I/O cache lines. As raw data is needed by the vector processor, whole DRAM rows are downloaded to the six lines of memory cache. The single-instruction multiple data vector processor rolls intermediate data around through the cache without causing it to write back to the DRAM. Any lines in the cache that will never be needed again, or that will be overwritten, are not written back. Any rows of data in the DRAM that will never be read or that will be overwritten are not refreshed. Each skipped read, write, or refresh of a row in the DRAM main memory saves significant battery power overall.Other References
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