Arbitrating multiprocessor accesses to shared resources
Fifo logical addresses for control and error recovery Patent #: 5760792
ApplicationNo. 729544 filed on 10/11/1996
US Classes:718/100, TASK MANAGEMENT OR CONTROL345/502, Plural graphics processors345/558First in first out (i.e., FIFO)
ExaminersPrimary: Banankhah, Majid A.
Attorney, Agent or Firm
International ClassG06F 009/00
AbstractA method and apparatus for preventing interference between simultaneously-running processes in a set top box processing system which attempt to access certain shared processing hardware such as a drawing acceleration engine. A graphics processor or other device such as a CPU associated with the processor includes a register with an acquire bit portion and a process identifier portion. When a given process requests access to a graphics engine or other shared processing hardware, a determination is made as to whether the acquire bit of the register is set. A set acquire bit indicates that some process has already been granted access to the engine. If the acquire bit is not set, the requesting process is granted access to the engine, and its process identifier is stored in the process identifier portion of the register. If the acquire bit is already set when the given process requests access to the engine, the identifier for that process is compared to the identifier stored in the process identifier portion of the register. If the identifiers match, the requesting process is granted access. The lack of a match between the identifiers indicates that a different process has previously been granted access to the engine, and the requesting process is therefore denied access to the engine. When a process granted access to the engine no longer requires access, the acquire bit is cleared.