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Abstract

The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.

Other References

• IEEE Electron Device Meeting Technical Digest, 1993, "Sub-50 NM Gate Length N-MOSFETS With 10 NM Phosphorus Source And Drain Junctions", M. Ono et al, pp. 6.2.1-6.2.4
• IEEE 1994 Custom Integrated Circuits Conference, "Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation", S. Sun et al, pp. 12.2.1-12.2.4
• P.J. Wright et al, "Thickness Limitations of SiO2 Gate Dielectrics for MOS ULSI", IEEE Transactions On Electron Devices, vol. 37, No. 8, Aug. 1990, pp. 1884-189