Semiconductor integrated circuit device
Patent 6307236 Issued on October 23, 2001. Estimated Expiration Date: 
October 6, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 6, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor integrated circuit device and process for manufacturing the same Semiconductor integrated circuit having a stand-by current reducing circuit Semiconductor integrated circuits with power reduction mechanism Semiconductor integrated circuit device having power reduction mechanism Semiconductor integrated circuit device having power reduction mechanism Patent #: 5614847 InventorsAssigneeApplicationNo. 155801 filed on 10/06/1998US Classes:257/392, Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode)257/402, With permanent threshold adjustment (e.g., depletion mode)257/406, Plural gate insulator layers257/410, Gate insulator includes material (including air or vacuum) other than SiO 2257/411, Composite or layered gate insulator (e.g., mixture such as silicon oxynitride)257/E21.623, Gate conductors with different gate conductor materials or different gate conductor implants, e.g., dual gate structures (EPO)257/E21.626, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E27.06, Field-effect transistor with insulated gate (EPO)257/E27.061Combination of depletion and enhancement field-effect transistors (EPO)ExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmForeign Patent References
International ClassH01L 029/72Foreign Application Priority Data1996-04-08 JPAbstractThe present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.Other References
Field of SearchInsulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode)With permanent threshold adjustment (e.g., depletion mode) Plural gate insulator layers Gate insulator includes material (including air or vacuum) other than SiO 2 Composite or layered gate insulator (e.g., mixture such as silicon oxynitride) | |
