Pipelined architecture to decode parallel and serial concatenated codes
January 26, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for implementing a maximum-likelihood decoder in a hypercube network Error-correction coding method with at least two systematic convolutional codings in parallel, corresponding iterative decoding method, decoding module and decoder Parallel concatenated tail-biting convolutional code and decoder therefor Method and coding means for protected transmission of data on the basis of multi-component coding Method and arrangement for determining an adaptive abort criterion in iterative decoding of multi-dimensionally coded information Communications systems and methods employing parallel coding without interleaving System for coding system Repetitive turbo coding communication method Hybrid concatenated codes and iterative decoding Error-floor mitigating turbo code communication method InventorsApplicationNo. 237714 filed on 01/26/1999US Classes:714/786, Forward error correction by tree code (e.g., convolutional)714/796Branch metric calculationExaminersPrimary: Decady, AlbertAssistant: Torres, Joseph D. Attorney, Agent or FirmInternational ClassH03M 013/03AbstractThe present invention provides a method and apparatus (400) for iteratively decoding data which has been encoded with contatenated codes. The apparatus (400) includes pipelined and cascaded decoder processors (406, 430 and 436) connected to a multiple block memory device (402), through a multiplexing and data control block (404). A data decision element (437) is provided for generating decoded output data. The method includes receiving encoded data (802) while data already received is processed iteratively by decoder processors in a pipelined fashion. Decoder processors are designated to perform particular iterations (810) of an iterative decoding process which are performed simultaneously. As a decoder processor completes processing its designated iteration on a block of data, the decoder processor outputs decoding information (808) to the decoding processor designated to perform the subsequent iteration. Upon completion of all iterations for a block of data, the method includes generating output (814) consisting of the decoded data block. The method provides that once processing is complete on a data block, the memory block is made available (816) for the storing of new encoded input data.Other References
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