Computer processor with instruction-specific schedulers
July 31, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-scheduling parallel computer system and method Single cycle dispatch delay in a multiple instruction dispatch mechanism of a data processing system Apparatus and method for distributed control in a processor architecture High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations Computer processor having a register file with reduced read and/or write port bandwidth Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time Operand dependency tracking system and method for a processor that executes instructions out of order Hardware instruction scheduler for short execution unit latencies Circuit and method for scheduling instructions by predicting future availability of resources required for execution InventorsApplicationNo. 126657 filed on 07/31/1998US Classes:712/215, Simultaneous issuance of multiple instructions712/23, Superscalar712/214, INSTRUCTION ISSUING712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/217Scoreboarding, reservation station, or aliasingExaminersPrimary: An, Meng-Ai T.Assistant: Lin, Wen-Tai Attorney, Agent or FirmInternational ClassG06F 015/82AbstractOne embodiment of the present invention is a computer processor that includes a first scheduler adapted to dispatch a first type of computer instructions, and a second scheduler coupled to the first scheduler and adapted to dispatch a second type of computer instructions. The first type of instructions all have a first latency and the second type of instructions all have a second latency. The first scheduler is skewed relative to the second scheduler so that when the first scheduler dispatches one of the first type of computer instructions having a first latency, the second scheduler will dispatch one of the second type of computer instructions that is dependent on the first type of computer instruction at a time equal to the first latency.Other References
Field of SearchHierarchical memoriesBubble memory Superscalar Simultaneous issuance of multiple instructions DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION Scoreboarding, reservation station, or aliasing Commitment control or register bypass Reducing an impact of a stall or pipeline bubble INSTRUCTION ISSUING | |
