Efficient and robust random access memory cell suitable for programmable logic configuration control
Patent 6292388 Issued on September 18, 2001. Estimated Expiration Date: 
June 28, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 28, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.InventorAssigneeApplicationNo. 606791 filed on 06/28/2000US Classes:365/156, Complementary365/154Flip-flop (electrical)ExaminersPrimary: Nelms, David C.Assistant: Tran, M. Attorney, Agent or FirmInternational ClassG11C 011/00AbstractA memory system with an operating voltage of Vcc has a memory cell with first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage controlled Vmm line. There is a passgate transistor connected source to drain from a BIT line to the first inverter, the passgate having a strength low enough that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch. Circuitry is provided for reducing the voltage of Vmm during a write cycle, so a signal on the BIT line may flip the latch. In preferred embodiments the memory system is applied to Programmable Logic Arrays. | |
